RF switches and power amplifiers represent two component RF devices that are commonly utilized in wireless communication devices (e.g., cellular or smart phones) to route high-voltage, low- and high-frequency signals through transmission paths between the device's processing circuitry and the device's antenna. For example, state-of-the-art attenuation and antenna tuning applications in such wireless communication devices require RF switches capable of transmitting RF signals up to 70V and in the range of 0.5 GHz to 6 GHz with a high degree of linearity. To accommodate the high-power RF signals, current state-of-the-art RF switches typically utilize several low voltage (e.g., 2-5V) NMOS transistors connected in a stacked (drain-to-source) arrangement such that the high RF signal voltage is distributed evenly across the low voltage transistors. With this arrangement, a first RF switch can be turned on to route high frequency signals from a wireless communication device's processing circuitry and a power amplifier circuit to an antenna during transmission-mode operations, and a second RF switch can be turned on to signals from the antenna to the wireless communication device's processor by way of a low-noise amplifier during receiving-mode operations.
RF switches that are produced using silicon-on-insulator (SOI) technology (referred to herein as RF SOI switches) were developed in response to a demand for low-cost solid-state RF switches for low-cost wireless communication devices. Silicon on insulator (SOI) technology refers to the use of a layered silicon-insulator-silicon substrate in place of conventional monocrystalline silicon substrates in semiconductor manufacturing, especially microelectronics, to reduce parasitic device capacitance, thereby improving performance. Early SOI technology was considered impractical for RF switch applications due to cutoff frequency and breakdown voltage problems, so early solid-state RF switches were typically generated using silicon-on-sapphire (SOS) and gallium-arsenide monolithic microwave integrated circuit (GaAs MMIC) technologies. However, due to advances in CMOS SOI technology that addressed the early problems, RF SOI switches produced using CMOS and SiGe BiCMOS flows (and in some instances using RF MEMS fabrication flows) are now recognized as achieving comparable operating characteristics to SOS and GaAs Monolithic microwave integrated circuit (MMIC) switches at a substantially lower cost. Moreover, because SOI technology uses standard technologies and standard cell libraries developed for CMOS, BiCMOS and RF MEMS fabrication flows, RF SOI switches can be integrated into larger system-on-chip (SOC) devices that further minimize fabrication costs.
RF SOI switches are field-effect transistor-type (FET-type) structures that are mainly distinguished from other FET-type transistors in that they are formed on/over isolated silicon pads (islands) of an SOI base substrate, but are otherwise produced using the same standard processes of the core (i.e., CMOS, BiCMOS or RF MEMS) fabrication flow that are utilized to simultaneously fabricate other circuit structures of a SOC device on the SOI base substrate. That is, the SOI substrate is typically processed using known techniques to generate spaced-apart silicon islands (i.e., portions of the topmost silicon layer that rests on and are surrounded by insulating material, typically silicon dioxide). The structural elements of the RF SOI switch are then fabricated onto an associated silicon island, typically using the same standard fabrication flow processes that are utilized to simultaneously generate other circuit structures of the SOC device. For example, the same standardized n-type or p-type dopant diffusion processes may be utilized to form source/drain regions in both the silicon island (i.e., for the RF SOI switch) and in other portions of the topmost silicon (e.g., to produce transistors forming a processor circuit or other functional circuitry of the SOC device). Similarly, the same polycrystalline silicon (polysilicon) gate structure formation processes (e.g., poly deposition, mask and etch) may be utilized to form the gate structures of the RF SOI switch, and to simultaneously form gate structures of the SOC device's functional circuitry. Next, the same pre-metal dielectric (PMD) layer formation process is typically utilized to form a PMD layer over the polysilicon gate structures of both the RF SOI switch and the other functional circuitry, and the same contact structure formation processes (e.g., mask, etch, metal deposition, and chemical mechanical polishing or other planarizing process) is typically used to form contacts to the source/drain regions in both the RF SOI switch and the functional circuitry. Subsequent backend processing (e.g., metallization and contact pad formation) is similarly simultaneously performed over both the RF SOI switch and the other functional circuitry of the SOC device.
As the demand for wireless communication devices capable of higher data-rate transmissions continues to grow, there is a concomitant demand for RF SOI switches that exhibit ever-improving operating characteristics. A conventional approach for improving the operating characteristics of an RF SOI switch is to minimize the switch's Ron·Coff, which is a common figure of merit used to rate the performance of RF switches. An RF SOI switch's Ron value is determined by measuring the resistance across the switch when turned on (e.g., in the NMOS case, when a high gate voltage is applied), and the RF SOI switch's Coff value is determined by measuring the capacitance across the switch when turned off. The Ron·Coff value is determined by multiplying a switch's measured Ron and Coff values, and therefore the operating characteristics of the RF switch can, in theory, be improved by way of adjusting the NMOS configurations to reduce one or both Ron and Coff values. That is, reducing the Ron value would allow more of the RF signal to travel through the RF switch when turned on, and reducing the Coff value would prevent more of the RF signal from traveling through the switch when turned off.
Conventional techniques for reducing Coff in RF SOI devices include the use of air gaps, which are gas-filled void regions that are intentionally introduced into a semiconductor structure. Air gaps have been used in semiconductor industry for reduction of inter-layer and intra-layer capacitance for many years. For example, U.S. Pat. No. 6,211,561 (Bin Zhao, 2001) describes patterning of voids in a dielectric layer deposited over a first level of interconnect lines, followed by deposition of a sealing layer over the voids, and then the deposition and patterning of a second level of interconnect lines. More recently, air gaps have been utilized to reduce Coff in RF SOI switches by way of displacing intermetal dielectric materials in regions over the switch's FET-type NMOS transistors, whereby capacitive coupling between the transistor' source and drain regions is reduced by way of replacing dielectric material higher dielectric constant values with air or another gas having a lower dielectric constant.
Conventional techniques for reducing Ron in RF SOI devices include the use of stressing layers (stressors), which typically comprise a dielectric layer that is disposed over the NMOS transistors' gate structures and intentionally fabricated to include a high residual tensile stress. Stressing layers function to reduce Ron in RF SOI devices by way of generating tensile mechanical stresses in the NMOS transistors' channel regions, thereby enhancing electron migration during operation.
Although air gaps and stressors may be utilized to respectively reduce an RF SOI device's Coff and Ron values, these two conventional techniques have proven to be incompatible when generated using conventional techniques. For example, FIGS. 13A and 13B are graphs respectively depict exemplary off-state capacitance values and exemplary on-state resistance values for RF SOI switches including intermetal air gaps and a 1200 Angstrom thick SiN stressing layer that are generated using conventional fabrication methods. FIG. 13A indicates that the combined use of air gaps and stressing layers significantly reduces the Coff value of RF SOI switches (i.e., in comparison to the zero-air-gap-width Coff value) by way of reducing off-state capacitance, and that the Coff value decreases in direct proportion to the air gap trench width. However, FIG. 13B indicates that the combined use of air gaps and stressing layers causes an increase in Ron (i.e., in comparison to the zero-air-gap-width Coff value), and that the Ron value further increases in relation to the air gap trench width. Therefore, because the decrease in Coff is effectively offset by a corresponding increase in Ron, conventional RF SOI switches do not include both conventional air gaps and conventional stressors.
What are needed are methods for improving the operating characteristics (e.g., Coff·Ron) of RF SOI devices. What is particularly needed are fabrication methods and associated RF SOI device structures that facilitate the combined use of both air gaps and stressors to reduce both Coff and Ron in an RF SOI device.